In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers and to increase the number of layers of such devices on a chip. In order to accomplish such high device packing densities, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Generally, the process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface.
The requirement of small features with close spacing between adjacent features requires sophisticated manufacturing techniques including dielectric layer deposition and planarization of the dielectric layer. Fabricating a semiconductor structure using such sophisticated techniques may involve a series of steps including cleaning, thermal oxidation or deposition, masking, developing, etching, baking and doping.